The present invention relates to techniques for programming and verifying data in a programmable circuit, and more specifically, to techniques for programming and verifying data in a programmable circuit that saves time and reduces the vector count.
Data bits can be programmed into memory cells of a programmable circuit during a program step. Subsequently, the accuracy of the data bits programmed into the memory cells can be verified during a verify step. Prior art techniques for programming and verifying data in a programmable circuit require an undesirably long delay time and a high vector count.
During a program step, a first set of address bits is shifted into row shift registers that selects the word lines, and a set of program data bits is shifted into column shift registers for each word line. During a verify step, a second set of address bits is shifted into the row shift registers that selects the word lines, and verify data bits are shifted out of the column shift registers for each word line.
Each word line is selected twice, once for programming data in each word line and once for verifying data in each word line. Also, the program data bits are shifted into the column shift registers separately from when the verify data bits are shifted out of the column shift registers. Thus, the number of times that data bits are shifted into and out of the column shift registers is twice the number of word lines.
If a second verify step is performed, a third set of address bits is shifted into the row shift registers that selects the word lines, and verify data bits are shifted out of the column shift registers for each word line. Thus, if two verify steps are performed, each word line is selected three times to perform the program step and the verify steps, and the number of times that data bits are shifted into and out of the column shift registers is three times the number of word lines.
Loading address bits and data bits into the registers separately each time program or verify steps are performed creates a high vector count and typically causes undesirably long program and verify time delays. It would therefore be desirable to provide a more efficient technique for programming and verifying data in a programmable circuit.